There are various kind of flat panel display devices characterized by low power consumption and small size. Those devices include the liquid crystal display (LCD), plasma display panel (PDP) and electroluminescence display (ELD). The LCD has been used in electron devices successfully because of its capability for high resolution. At present, the portable computer or personal data assistant (PDA) are widely used in the mass market and those are remarkably progressing. In order to meet the requirement of portable apparatus, the displays for portable use are light weight and low power consumption. Thin film transistor-liquid crystal display (TFT-LCD) is one of the devices that can fit the aforementioned requirements and is known as the display required for the high pixel density and quality.
In general, the TFT-LCD includes a bottom plate formed with thin film transistors and pixel electrodes and a top plate formed with color filters. The liquid crystal is filled between the top plate and the bottom plate. In each unit pixel, the TFT serves as a switching element of the unit pixel. When the data voltage is applied to the TFT, the arrangement of the liquid crystal molecules is changed, thereby changing the optical properties and displaying the image. The color filter (CF) plate is used in the LCD to show the colored portion of the screen.
In the art, two types of the TFT structure are developed. One is the so called ES (etching stopper) TFT and the other one is the BCE (bask channel etched) TFT. In the type of BCE TFT, there is no etching block on the channel region, therefore, the channel region will be etched during the process because of the etching rates of the amorphous silicon and the doped silicon are similar. Please refer to FIG. 2, a gate electrode 22 is formed on the substrate 20. An insulating layer 24 is next formed on the gate electrode 22. An amorphous silicon layer 26 having a channel loss region 26a is over the insulating layer 24. The amorphous layer 26 has a doped silicon layer 28 formed on a portion of the amorphous silicon layer 26 for forming ohmic contact. Source and drain (S/D) electrodes consisting of a Cr 29a sub-layer and an Al sub-layer 29b are patterned on the doped silicon layer 28. The disadvantage of the BCE type structure is that the channel region will lose thickness during the etching for forming the S/D electrodes. In addition, the wet etching to etch the double metal (Al/Cr) layers generates undercut portions 29c under the Al sub-layer 29b due to the etching rate of the two sub-layers is different and the solution will laterally etch the Cr layer. It is hard to control the etching conditions to prevent the channel from being etched and forming the undercut portions 29c.
Referring to FIG. 3, in the type of the ES TFT structure, an etching stop layer is formed over an amorphous silicon layer to prevent the channel region formed in the amorphous silicon layer from being etched while an etch is performed to form the source and drain. The ES type is shown in FIG. 3, the structure includes a substrate 32, a gate electrode 34 is formed on the substrate. An insulating layer 36 is formed on the gate electrode 34 for isolation. An amorphous silicon layer 38 is patterned on the isolation layer 36. Reference number 42 is the aforementioned etching stopper 42 to protect the channel region. Thus, it has high resistant to etch. Source and drain (S/D) electrodes 44 are formed on the amorphous silicon layer 38 and a portion of the etching stopper 42. Typically, the S/D electrodes 44 are consisted of multi-metal layers, which are n+ doped silicon layer 44a, a first titanium layer 44b , an aluminum layer 44c and a further titanium layer 44d. The n+ doped silicon layer 44a is used to form ohmic contact layer. In the structure, a portion of the ES layer 42 is exposed by the S/D electrodes 44. The channel region under the ES layer 42 will not be attacked during the etching to form S/D electrodes 44. However, the channel length of the ES type TFT is longer than BCE type TFT structure.
As the display resolution is going higher and higher, the performance of the TFT is also pushed higher and higher. From the device performance point of view, the BCE type TFT has the advantage of shorter channel length. Considering the channel loss, wet etch of the S/D metal is preferred. However, a multi-layer structure is usually applied for the source and drain metal. As shown in FIG. 1, a triple-layer 4 consists of a first barrier metal 4a, a major conducting layer 4b (usually Al) and a second barrier metal 4c, such as a Mo/Al/Mo structure. In order to obtain a taper etching profile, the etching rate of the metal layer 4a must be higher than that of Al. Because 4c is usually similar to 4a, it is easy to form an Al overhang structure as shown in FIG. 1, which is not a healthy profile. Furthermore, the channel length is determined by the CD of the layer 4c, which is the CD defined by the photoresist plus the side etch of the Al and layer 4c. As a result, the BCE TFT performance is strongly degraded.
Thus, what is required is a novel method to form the TFT to avoid aforementioned disadvantages of BCE and ES TFT.